77981_IP Verification Manager
Advanced Micro Devices
Shanghai, Shanghai, CN

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP subsystem for all AMD products including dGPU, APU, Server and Game consoles, NBIO subsystem provides PCIe connectivity to external devices as well as AXI-based IPs.

NBIO global team operates seamless from China, North America and Europe.

NBIO subsystem team are expanding, we are looking for a NBIO subsystem DV manager based in Shanghai. He / she is responsible for managing NBIO subsystem DV team, co-work closely with global NBIO subsystem DV team, develop and verify NBIO subsystem.


Candidate will manage a DV team with more than 15 team members, need to have solid DV background and more than 2 years’ team management experience, fluent spoken English and very good communication skill in both English and Chinese.


  • Strategic team development plan
  • Talent recruit and internal talent grow
  • Inspiring innovation
  • Project execution tracking and signoff
  • NBIO subsystem schedule negotiation
  • Global communication and alignment.
  • Team performance management
  • Short term global travel upon business need

  • Global company working experience, fluent oral English
  • Direct people management experience no less than 8 in team size
  • Good communication skills in both Chinese and English
  • Complex IP / ASIC / SOC design verification background, direct experience in IP / SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort)
  • Solid background with ASIC design verification flow and multiple ASIC tape out experience
  • Solid knowledge on SystemVerilog, C / C++, Verilog
  • Solid knowledge on scripting language like perl, python, ruby
  • Solid knowledge on UVM / OVM
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
  • Knowledge on USB or PCIE is a big plus
  • Experience in project management is a big plus

  • MSEE with minimum of 8 years, or BSEE with minimum of 10 years’ experience in digital ASIC / SOC design verification
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