ASIC Digital Design Engr, II
Synopsys, Inc
CHINA - Wuhan
32天前

Job Description and Requirements

As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop ATPG and DFx validation platform.

Position Responsibilities :

  • Participate in the discussions / reviews of the regression results to improve the correct and efficiency of the ATPG and DFx flow
  • Be responsible for ATPG pattern generation with good DFT fault coverage
  • Requirements :

    Must have BSEE in EE with 5+ years of relevant experience or MSEE with 3+ years of relevant experience in the following areas :

  • Demonstrates good communication skills in English
  • Good skills in scripting and automation
  • Experiences with DFT and ATPG
  • Knowledge of Verilog and IC design development cycle
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