Senior Mask Layout Engineer

Job Overview : - Design analog standard cell library of different process - Design and maintain pad library for both analog IP and P&R team - Meet project milestone deadlines - Independently debug drc, lvs, erc, antenna, soft check and short issues - Follow circuit designers expectation and can place good floorplan, routing consideration, estimate schedule, save area etc.

JOB RESPONSIBILITIES : -Apply your analog integrated circuit design and verification expertise to the development of mobile communication systems and wired peripherals.

Circuits of interest are : ADCs, DACs, VCO / PLLs, Sigma-Delta Modulators, continuous time and switched-cap filters, Audio class D / G / H amplifiers, voltage regulators and precision references, High speed SerDes Transmitters and Receivers.

Low voltage and low power CMOS design techniques in nanometer technologies are emphasized. -Perform analog and mixed-signal modeling and verification tasks, both at IP and chip level.

  • Work together with layout engineers to optimize circuit performance. -Trouble-shooting and debug in Labs. Qualifications : - Outstanding English written and verbal communication - 2 years' experience in analog / mixed-signal layout - Custom layout experience can include standard cells library layout design, memory design, analog block level layout, such as PLL, ADC, DAC, Bandgap, LDO etc.
  • Familiarity with Cadence Virtuoso tool and layout-XL - Experience including one or more process nodes : 0.18um, 65nm, 40nm, 28nm - Excellent communication skills and teamwork All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
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