At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Physical implementation and verification engineer
Job Description :
A role of block / chip level physical design engineer;
Job content includes :
Physical Design, including : floorplan, placement, CTS, routing, etc. ;
Static Timing Analysis;
EM / IR Analysis.
Job Qualification :
Rich knowledge of the design rule for the process of N28 / N16 and below;
Ability of fixing the physical design violations, including : DRC, DFM, LVS, ANT, ERC etc.;
Experience in chip level physical verification is preferred;
Basic knowledge / experience of the physical implementation and static timing analysis;
Bachelor or above degree in majors of EE / CS / IT, with more than 3 years’ work experience;
Good ability of effective learning and independent thinking;
Good ability of communication and teamwork;
Carefulness, responsibility and persistence.
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