GLOBALFOUNDRIES Layout Design Engineers at are responsible for circuit layouts development for our industry-leading Design or IP offerings, including SerDes, memory, etc.
By employing the industry leading tools, state of the art methodology, and innovative semiconductor cutting-edge technologies ranging from 14nm and beyond, the layout design engineer is responsible of the floor planning, physical design and verifications.
1. BS and above in Electrical or Related Areas.
2. Good understanding of advanced semiconductor technology process and device physics.
3. Full-custom circuit layout / verification and RC extraction experience. Experiences in one or more of
the following area is preferable :
Mixed signal / analog / high speed layout, e.g. SerDes, ADC / DAC, PLL, etc.
High performance / capacity memory layout, e.g. SRAM, RF, RA, etc.
4. Familiar with Cadence Virtuoso environment and various industry physical verification tools
5. Experiences in advanced technology node under 32nm / 28nm / 16nm / 14nm and FinFET is
6. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable.
7. Good English skills, communication skills, and willingness to work with a global team.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and