As a package designer, you will be responsible for advanced package design and technology development, as well as foundry management and vendor interfacing.
You responsibilities include, but not limited to :
Design rule development and implementation of in-house packaging layout to meet product requirements.
EDA tool set up and flow development.
PI / SI analysis on full chip and critical IPs at package and board level.
Define and develop package solution for high speed, high power and large pin count device in a cross-function team
Collaborate with foundry, PE, TE and QA teams on chip bring up and qualification.
Interface with vendors on process optimization, chip characterization and failure analysis for volume production
Drive new technology development such as multi-die, hybrid-bonding, advanced substrate, design for manufacturability and design for reliability, as a collaborative effort with vendors
Master’s degree and / or PhD in Electrical Engineering or related fields with 5+ years of experience.
Hands on experiences the following : Cadence Allegro APD & SiP tools, Sigrity XtractIM, PowerSI
Hands on experiences with layout of FCBGA, MCM, SiP, WLBGA etc and optimization for ball count and power grid.
Experience on design of very large form factor flip chip package with high substrate layer count
Experience on 2.5D or 3D multi-die solutions such as Info, CoWoS, SoIC or chiplet.
Experience with high-speed IO interfaces design and bringup such as DDR, PCIe and HBM is preferred.
Experience on mechanical and thermal analysis and control, knowledge on mechanical and thermal reliability is a must.
Understanding of voltage regulator design and power distribution is a plus.
Capability of driving package roadmap to meet future products on advanced nodes.