Principal Design Engineer
Cadence Design Systems, Inc

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description :

  • Co-work with the R&D RTL design team for IP architecture exploration and optimization of the design and constraint
  • Co-work with other functional teams (Design / STA / Analog / Package / Verification) to optimize the high speed PHY IP development flow and set proper signoff criteria.
  • Optimize the physical implementation methodology and flow to meet the tight timing / power target of next generation high speed PHY IP.
  • Set and optimize the high speed PHY IP physical implementation guide which will be used by customers and internal global physical implementation teams.
  • Perform physical design implementation tasks including floor planning, place&route, clock tree synthesis and Timing / PV / Power / Signal-
  • EM / CLP / DFM signoff checks for some critical milestone projects.

    Position Requirements :

  • BS degree with 5 10+ years of applicable experience, MS degree with 4 8+ years of applicable experience in electrical engineering, microelectronics.
  • Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-
  • micron technology issues.

  • Solid knowledge on LP Design, static timing analysis, EM / IR-Drop / crosstalk analysis, physical verification, DFM.
  • Successful track records of taping out complex, 16nm / 10nm / 7nm chips.
  • Automation and programming-minded, solid coding experience in Makefile / Tcl / Tk / Perl.
  • Innovative, self-motivated, able to work independently or as a team player.
  • Excellent verbal and written communication skills in English.
  • We’re doing work that matters. Help us solve what others can’t.

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