Lead Physical Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description :

  • Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power / signal integrity signoff, physical verification (DRC / LVS / Antenna), EM / IR signoff, DFM Closure.
  • The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design.
  • The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

    Position Requirements :

  • BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
  • Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
  • Solid knowledge on LP Design, static timing analysis, EM / IR-Drop / crosstalk analysis, physical verification, DFM.
  • Successful track records of taping out complex, 16nm / 10nm / 7nm chips. Automation and programming-minded, solid coding experience in Makefile / Tcl / Tk / Perl.
  • Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.
  • We’re doing work that matters. Help us solve what others can’t.


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