1. 4G / 5G modem architecture and digital circuit design
2. Whole chip clock, test, and reset plan.
3. Low power digital design
4. SoC chip integration from RTL to gate level including timing closure and testability
5. Design methodology and integration flow improvement
Requirement 1. Better to have chip integration experience
2. Familiar with front-end or back-end implementaion flow and related EDA tools
3. Familiar with clock tree power analysis flow
4. Familiar with SoC platform architecture including MCU, Bus, Cache, and DRAM controller
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