As a member of the design team, you will build the next generation networking SoC in advanced process. You will be the SoC Technical lead and representative interfacing with different IP blocks such as CPU core, DSP DDR controller, PCIE.
You responsibilities include, but not limited to :
Define and lead implementations of SoC top level architecture such as IP integration SMMU(systemMMU), PMU (power management), interrupt subsystem, fabric, global timer, cache coherence protocol, and so forth.
Interface with the physical design team and be responsible for integrating subsystems at full chip level and deliver the RTL to backend team for physical design
Interface with the DV team to draft SoC top level verification plan. Define function coverage point and provide debug perspectives for SoC top level verification.
Help to create top level SPECs such as SDC, UPF plan etc.
Work closely with design and PD team to optimize PPA
Successful candidates should meet one or more of the following requirements :
BS or MS of EE, 5-10 years of experience on SoC architecting.
Experience with ARM-based SoC integration
Strong background of computer architecture
Familiar with PCIe, DDR architectural protocol
Familiar with popular on-chip cache coherence protocol (e.g., MESI or MOESI)
Familiar with popular on-chip interconnect protocol (e.g., AMBA AXI, OCP, TileLink, etc.)